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 Wednesday, March 21 2018 @ 05:51 CET


NewsFPGArduino transform popular FPGA development boards into microcontroller systems programmable using the intuitive Arduino development environment.

The SoC is based on the f32c CPU core which was originally designed to execute a subset of the MIPS instruction set. So far the f32c CPU can be configured to execute the RV32I subset of the RISC-V ISA, except performance counter accessors which we omitted as unessential.

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Authored by: tingo on Saturday, April 29 2017 @ 18:23 CEST
RISC-V is now also available on IGLOO2 FPGAs from Microsemi: RISC-V Instruction Set Architecture.
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